Random Access Memory using Logic Gates

In our previous blog post, “Binary Additions using Logic Gates”, we investigated how logic gates can be used together to create a circuit used in the ALU (Arithmetic & Logic Unit of the CPU) to add two binary numbers together.

In this blog post we will investigate how logic gates are used to create the RAM (primary memory), in other words how logic gates can be used to store volatile information.

Random Access Memory

Random Access Memory (RAM) is volatile memory that sits next to the CPU. (Volatile means that it is wiped out when the computer is switched off). It is used to store instructions and data currently used by the CPU.

RAM consists of billions of Data Cells, each data cell being able to store one bit of information. For instance a 2GB RAM can store 2,000,000,000 Bytes of information = 16,000,000,000 bits of information and hence consists of 16,000,000,000 data cells.

D-Type Flip-Flop Circuits

Each data cell consists of a D-Type Flip-Flop circuit that is built using four NAND logic gates connected as follows:


We represent a D-Type Flip-Flop Circuit as follows. You can change the input values D and E by clicking on the corresponding buttons below to see the impact on the outputs Q and Q.

You can also test the behaviour of a D-Type flip-flop circuit using our online simulator:
Click on the above circuit to open in a new window.

A D-Type Flip-Flop Circuit is used to store 1 bit of information. It has two input pins (Called D (Data) and E (Enabler) and two output pins (Q and Q = NOT Q).

The truth table of a D-Type Flip-Flop circuit is as follows:

When the enabler input E is set to 1, the output Q can be set to the Data input D.
When the enabler input E is set to 0, the output Q cannot be changed. It remains as its previous value. In other word it retains its value. This is why this circuit is used to create memory cells (e.g in the RAM).

Clock Signal and Delaying Effect

The enabler input E is often connected to another circuit called the clock (e.g. CPU clock). The clock signal constantly and regularly alternate between two states: 0 and 1, similar to a heart beat. Inside the CPU the clock signal controls the execution of the FDE cycle.

When the clock signal is applied to the Enabler input (in this case also called the clock input), the flip-flop output Q can only change values when triggered by the clock signal. The value of the flip-flop is held or delayed until the next clock signal. This delaying effect is also called a latch. This is why we call this circuit a D-Type flip flop where D stands for Delay.

In other words, the change of input (D) is not applied immediately (to the output Q) but is applied at the next “tick of the clock”. There are many applications to this delay such as the ability to create a frequency divider. (divide the clock frequency by a multiple of 2).