Understanding Memory Address Modes

There are many ways to locate data and instructions in primary memory and these methods are called “memory address modes”.

Memory address modes determine the method used within the program to access data either from the Cache or the RAM.
In this challenge we will focus on four different memory address modes:

• Immediate Access
• Direct Access
• Indirect Access
• Indexed Access

We will use LMC programs to see how these modes can impact on the output or flow of a program. Remember, with LMC (or any assembly languages) an instruction consists of an opcode followed by an operand.
For instance:

• Instruction: ADD 7
• Opcode (using a mnemonic): ADD
• Operand: 7

Memory address modes enable us to provide either a hard coded value or a memory location for the operand.

So let’s recap on the difference between these memory address modes.

Immediate AddressingDirect AddressingIndirect AddressingIndexed Addressing

Immediate Addressing

Immediate addressing means that the data to be used is hard-coded into the instruction itself. For instance:

ADD 7

Nothing needs to be fetched from memory. This instruction means that the value 7 will be added to the value currently stored in the accumulator.

This is the fastest method of addressing as it does not involve fetching anything from the main memory at all.

Direct Addressing

Direct Addressing is a very simple way of addressing memory – it means that the operand of an instruction refers directly to a location in memory.

For example:

ADD 7

This instruction would not add the value 7 to the accumulator. Instead it would add the value currently stored at memory location 7 (that will be need to be fetched from the Cache/RAM).

The online LMC simulator uses this memory address mode.

This memory address mode is fairly fast (not as fast as immediate addressing though).

Indirect Addressing

Indirect addressing means that the address of the data is held in an intermediate location so that the address is first ‘looked up’ and then used to locate the data itself. Fetching the value is a two step process: First the indirect address is used to locate an entry into a lookup table (called Vector Table) where the actual address of where the value can be fetched from is stored.
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So, indirect addressing mode is a two steps process: the operand is an address towards a memory location that contains an address where the value can be fetched from.

Indexed Addressing

Indexed addressing means that the final address for the data is determined by adding an offset to a base address.

This memory address mode is ideal to store and access values stored in arrays. Arrays are often stored as a complete block in memory (A block of consecutive memory locations). The array has a base address which is the location of the first element, then an index is used that adds an offset to the base address in order to fetch the specified element within the array.

Your Challenge

For a language like LMC, when using the online simulator, we know that only direct addressing is used.

However if we had a choice between several memory address modes, we need to find a way to specify which mode is used by an instruction.

This can be done by using a specific character.
For instance, “#” could be used to represent immediate addressing, “&” could be used to represent direct addressing, “~” for indirect addressing and “[]” for indexed addressing.

In this case there is no room for confusion to understand which memory address mode is used. e.g.

ADD #7
ADD &7
ADD ~7
ADD 7[2]

In the following challenges, we will use the notation mentioned above. Your task is to predict the output of these short programs.

Note: This notation is not an official notation. It should only be used to solve the challenges listed below.

LDA &8
ADD #4
OUT
HLT
6
2
10
15
16
17

LDA &8
ADD &5
OUT
HLT
6
2
10
15
16
17

LDA &8
ADD ~5
OUT
HLT
7
1
10
15
13
22

LDA #7
ADD &6
OUT
HLT
6
2
10
15
16
17

LDA ~5
ADD ~5
OUT
HLT
7
2
10
15
16
17

LDA #5
ADD 7[0]
OUT
HLT
9
3
10
15
16
17

LDA #5
ADD 7[2]
OUT
HLT
6
2
10
15
16
17

LDA ~5
SUB #5
OUT
HLT
7
2
10
15
16
17